Semiconductor manufacturing provides lithography processes for patterning mechanical and electronic elements along two lateral directions of a main surface along which the mechanical and/or electronic elements are formed on a semiconductor wafer. Semiconductor devices like MEMS (micro electromechanical systems) and state of the art integrated circuits like Power MOSFETs (Power metal oxide semiconductor field effect transistors) are further based on patterning processes effective for shaping mechanical or electronic structures along a dimension vertical to the main surface. Conventional patterning processes which are effective in the vertical dimension make use of anisotropic deposition processes, depletion of precursors in trenches in a gaseous process environment and shadowing effects in case of tilted ion beam etching or tilted implants, by way of example. Conventional vertical patterning processes are either typically constricted to certain process materials/topologies or are difficult to control across a complete wafer surface or among the wafers of a wafer lot. There is a need for precise vertical patterning methods.